mitsubishi digital assp ? M66007P/fp 12-bit input expander 1 mitsubishi digital assp ? M66007P/fp 12-bit input expander description the m66007 is a semiconductor integrated circuit providing the 12-bit parallel input-serial output shift register function. this product is completely designed with cmos to sharply reduce power consumption compared with bipolar or bi- cmos product. the m66007, developed as an input only expander ic neces- sary for microcomputer periphery, is widely applicable as a data parallel/serial conversion ic. features ? control signals of only two pins including le/d and clk ? low power consumption of 50 w/package maximum (vcc=5v, ta=25c at time of standstill) ? schmitt triggered input (le/d, clk, d0 to d11) ? wide operating supply voltage range (vcc=2~6v) ? wide operating temperature range (ta=C20~75c) application parallel/serial data conversion for microcomputer periphery function the m66007 uses a silicon gate cmos process to achieve low power consumption and high noise margin. for control signals, this ic adopts only the two pins of latch input/serial data output le/d and clock input clk. each bit of shift register of 12-bit parallel input-serial output consists of flip-flop for shift. when le/d is placed in input mode, clk is set to h and le/ d changes from h to l, the status of parallel data inputs d0 to d11 at that time is latched with the flip-flop for shift and le/ d is switched to output mode to output l. pin configuration (top view) block diagram outline 16p4 16p2n-a after this, change of clk from h to l makes the shift regis- ter perform shift operation and le/d outputs the contents of the shift register from d0 in order. in addition, the shift operation for up to the 12th bit is carried out and then le/d is switched to the input mode at the falling edge of clk of the 13th bit. when power is turned on, the input/output mode of le/d is indeterminate. however, detection of 13 or more falling edges of clk sets le/d in the input mode. le/d clk d11 d10 d9 d8 d7 d6 d5 d0 d1 d3 le/d ? clk ? d0 ? d1 ? d2 ? d3 ? d4 ? gnd v cc ? d11 ? d10 ? d9 ? d8 ? d7 ? d6 ? d5 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? y ? ? ? ? ? ? ? ? ? t latch input/ serial data output 116 215 314 413 512 611 710 89 parallel data input clock input parallel data input d2 d4 1 2 8 16 15 14 13 12 11 10 9 7 6 5 4 3 d 11 d 10 d 9 d 8 d 0 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 q 11 q 10 q 9 q 8 q 0 gnd vcc clk le/d vcc q p lclk q n clk sq sd le le d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 latch input/ serial data output clock input parallel data input parallel latch shift register control circuit
2 mitsubishi digital assp ? M66007P/fp 12-bit input expander description of operation (1) when power is turned on, le/d is placed in input/output indeterminate mode. however, detection of 13 or more of falling edges of clk sets le/d in input mode. (2) when le/d is placed in input mode, and clk is set to h, access starts at a falling edge of le/d and the status of d 0 to d 11 is latched. (3) in addition, le/d switches from input mode to output mode and then outputs l. operation timing chart (4) at a falling edge of clk from h to l, data latched in step (2) is shifted sequentially and is then output from le/d in order of d 0 to d 11 . (5)after the output of 12-bit data of d 0 to d 11 , le/d is switched to input mode at the 13th falling edge of clk to wait for next access. keep the le/d pin set to h until the next access starts. 1 23 4 5 6 7 8 9 10 11 12 13 d 0 clk (in) (out) ? ? ? ? ? ? ? ? ? ? ? ? ? le/d d 11 d 0 ~ d 11 d 0 le/d input/output mode power on ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? rest sequence (13 clocks or more) (2) (4) (3) (1) input/output indeterminate indeterminate input mode (latch signal) output mode (output signal) input mode d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 (5)
mitsubishi digital assp ? M66007P/fp 12-bit input expander 3 conditions v o =0.1v, v cc C0.1v, i o =20a v o =0.1v, v cc C0.1v, i o =20a v i =v t+ , v tC v cc =4.5v v i =v t+ , v tC v cc =4.5v v i =v t+ , v tC v cc =6v v i =v cc , gnd, v cc =6v, le/d=h v i =v cc , gnd, v cc =6v, le/d=l conditions v i <0v v i >v cc v o <0v v o >v cc v cc, gnd ratings C0.5 ~ +7.0 C0.5 ~ v cc + 0.5 C0.5 ~ v cc + 0.5 C20 20 C20 20 20 C60 ~ 150 symbol v cc v i v o i ik i ok i cc t stg parameter supply voltage input voltage output voltage input protection diode current output incidental diode current power/gnd storage temperature unit v v v ma ma ma c absolute maximum ratings (ta = 20 ~ 75c unless otherwise noted) recommended operating conditions symbol v cc v i v o t opr parameter supply voltage input voltage output voltage operating temperature limits min. 2 0 0 C20 typ. max. 6 v cc v cc 75 unit v v v c symbol v t+ v tC v ol v oh i o i cc parameter threshold voltage in positive direction threshold voltage in negative direction low-level output voltage high-level output voltage maximum output leak current static consumption current electrical characteristics (vcc = 2 ~ 6v unless otherwise noted) limits max. 0.8 v cc 0.65 v cc 0.1 0.5 10.0 C1.2 100.0 1.2 min. 0.35 v cc 0.2 v cc 4.4 4.0 max. 0.8 v cc 0.65 v cc 0.1 0.4 1.0 C0.8 10.0 0.8 typ. unit v v v v a ma a ma min. 0.35 v cc 0.2 v cc 4.4 4.1 t a =25?c t a = C20~75?c i ol =20a i ol =1ma i oh =C20a i oh =C1ma v o =v cc v o =gnd symbol f max t plh t phl t plz t phz parameter maximum repetition frequency output l-h, h-l propagation time clk-le/d output l-z, h-z propagation time clk-le/d switching characteristics (vcc=5v) unit mhz ns ns ns ns limits max. 400 400 400 400 typ. min. 2 c l =50pf (note 1) t a = C20 ~ 75?c conditions
4 mitsubishi digital assp ? M66007P/fp 12-bit input expander parameter clk pulse width le/d pulse width (input mode) clk set up time for le/d d 0 ~d 11 set up time for le/d clk hold time for le/d d 0 ~d 11 hold time for le/d timing requirements (v cc = 5v) limits note 1. test circuit symbol t w t su t h unit ns ns ns max. typ. min. 250 250 100 100 200 200 conditions t a = C20 ~ 75?c (1) characteristics (10%~90%) of pulse gen- erator (pg) t r = 6ns, t f = 6ns (2) electrostatic capacitance c l includes the floating capacitance of connection and probe input capacitance. sw2 open open open close item t plh t phl t plz t phz sw1 open open close open dut v cc v cc input r l =1k w gnd pg 50 w c l sw1 sw2 r l =1k w le/d
mitsubishi digital assp ? M66007P/fp 12-bit input expander 5 timing diagram 50% clk 50% 50% 0v 50% le/d (out) t plz t pzl t w + t w C 50% 50% 50% 50% v cl v ol v cc v oh v cc v cc d 0 ~d 11 led (in) clk 10% t plz t su t h 50% t phz 90% output mode le/d le/d input mode 0v v ol 50% 50% t w C 10% t su t h 0v 0v v cc 0v clk
6 mitsubishi digital assp ? M66007P/fp 12-bit input expander precautions for application 1. the following timing diagram shows the status of mcu port and le/d pin of the m66007 when power is turned on. when mcu has been reset to make the collision period of mcu and le/d line of the m66007 as short as possible, place the port (le/d) in input mode and execute the reset sequence through the port (clk) promptly to reset the m66007. as shown in the diagram, to prevent the ic from being bro- ken due to collision of the le/d line in the 1-2 section, set in the le/d line in series a resistance of a degree to which the transmission speed cannot be affected. 2. when the le/d pin on each of the mpu and m66007 sides switches from input mode to output mode or from output mode to input mode, the le/d pin may be placed in high impedance status, resulting in oscillation. to prevent malfunction due to this oscillation, pull up the le/d line with a high resistance of a degree to which v oh and v ol levels cannot be affected. (with approx. 20k w pull- up resistance built-in) status of mcu and m66007 with power turned on connection example of mcu and m66007 power on mcu reset m66007 reset sequence m66007 reset mcu port (data) input/output indeterminate input/output indeterminate input mode output mode input mode input/output indeterminate input/output indeterminate output mode mcu port (clk) 13 clocks or more m66007 le/d 1 2 3 serial resistance port (data) port (clk) mcu i/o=le/d i=clk m66007 pull-resistance
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